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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:22:58 10/28/2013 
-- Design Name: 
-- Module Name:    Instruction_Mem - Behavioural 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Instruction_Mem is
    Port ( clock : in STD_LOGIC;
			  address : in  STD_LOGIC_VECTOR (7 downto 0);
           data : out  STD_LOGIC_VECTOR (31 downto 0));
end Instruction_Mem;

architecture Behavioral of Instruction_Mem is
	 
	 constant START_OFFSET 	: std_logic_vector 	:= X"0040000";
	 
	 type rom_type is array (0 to 255) of std_logic_vector (7 downto 0);                 
    constant ROM : rom_type:= (X"00", X"00", X"00", X"00",
										 X"00", X"00", X"00", X"00",
										 X"00", X"00", X"00", X"00",
										 X"00", X"00", X"00", X"00",
										 X"00", X"00", X"00", X"00",
										 X"00", X"00", X"00", X"00",
										 X"00", X"00", X"00", X"00",
										 X"00", X"00", X"00", X"00",
										 X"00", X"00", X"00", X"00",
										 X"00", X"00", X"00", X"00",
										 X"00", X"00", X"00", X"00",
										 X"00", X"00", X"00", X"00",
										 others => X"00");

begin

process (clock)
	variable convAdd : STD_LOGIC_VECTOR (7 downto 0);
begin
	if clock = '1' and clock'event then
		convAdd := address - START_OFFSET;
		data <= ROM(conv_integer(convAdd)) & ROM(conv_integer(convAdd+1)) & ROM(conv_integer(convAdd+2)) & ROM(conv_integer(convAdd+3));
	end if;
end process;
end Behavioral;

